Low AC Impedance Input Stages are widely used in a variety of applications including linear and low-dropout voltage regulators (LDOs), high performance opamps, and a variety of applications requiring current-mode amplification stages. Typical prior art implementations of low AC impedance input stages suffer from slow startup problems due to the presence of an undesired DC path between the positive and negative inputs of the input stage. This undesired DC path results in very slow startup times in applications which may require fast startup times (e.g. LDOs, and Opamps). The slow startup problem present in typical prior art implementations of the low AC impedance input stage is explained below.
FIG. 1 shows a typical prior art implementation of a PMOS based low AC impedance input stage. The stage consists of four P-channel field effect transistors (FETs) MP1–MP4, and a tail current bias I1 for two of the four FETs MP2 and MP3. FETs MP2 and MP3 are equally-sized diode connected FETs such that the combined drain currents of FETs MP2 and MP3 are equal to the tail current 2I. Under perfectly balanced conditions the voltage on input node V+ equals the voltage on input node V−, and the current on output node I+ equals the current on output node I−. A small input differential voltage of 2•V (•V on the V+ pin and −•V on the V− pin) creates a small output differential current of 2•I (•I on the I+ pin and −•I on the I− pin). The differential currents typically go to the common gate devices in a folded cascade gain stage but can also be used in a wide variety of arrangements to realize gain. The slow startup problem in this stage is caused by the following scenario: Suppose at the instant of startup a buffer is driving the V+ pin while the V− pin is at ground (e.g. through the presence of a significant capacitive load at the V− node). This will activate the parasitic DC path from node V+ through the diode connected FET MP2, through the body diode of FET MP3, (activated as the drain of FET MP3 goes above the bulk of FET MP3) to node V−, essentially creating a short between nodes V+ and V− upon startup. This parasitic path, shown in FIG. 1, would significantly overload any buffer driving node V+, and therefore significantly slow the startup transient. It could also cause any buffer driving node V+ to oscillate due to the sudden activation of this parasitic DC path and the load that this would present to the driving buffer.
In a typical high-input-impedance differential pair where the input signal is coupled to the gate of the input FETs, no such parasitic path exists due to the high input impedance present at the input pins. The speed-to-power ratio, however, in a standard high-input-impedance differential pair input stage is significantly worse than that in a low-impedance input stage, which is why the use of low-impedance input stages is on the increase in low power applications.